Methods of recording and reproducing and apparatus for recording and reproducing time codes

ABSTRACT

A supplied time code is multiplied to generate detailed time data. The detailed time data are latched at a given time in an input signal. The latched time data are converted into converted time data having a given data format. The converted time data are recorded in the same transmission path as the output signal.

This is a National Stage of PCT/JP95/01054.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods of recording and reproducingand apparatus for recording and reproducing time codes for use in a datarecorder, for example.

2. Description of the Related Art

Data recorders, for example, are occasionally required to reproduce atime at which an optional event or the like observed in recorded datahas occurred. To meet such a requirement, it has heretofore beencustomary for a data recorder to record time codes together with data.Time codes established by the IRIG (Inter-Range Instrumentation Group)in the USA, for example, have been used as such time codes for datarecorders.

The time codes of IRIG include two types of time codes, i.e., time codesof IRIG(A) and IRIG(B). These time codes will first be described below.The main difference between the time codes of IRIG(A) and IRIG(B) liesin minimum units of the time codes. The minimum unit of the time code ofIRIG(A) is 0.1 second!, and the minimum unit of the time code of IRIG(B)is 1 second!.

FIG. 1 of the accompanying drawings shows the time code of IRIG(A). InFIG. 1, the time code of IRIG(A) includes codes for "0.1 second","second", "minute", "hour", and "day" which are represented by numericalvalues according to the binary-coded decimal notation.

As shown in a lower portion of FIG. 1, the time code of IRIG(A) isgenerated by modulating a carrier signal of 10 kHz. A bit clock pulse isgenerated every 10 cycles of the carrier signal, i.e., every 0.001second. 100 bits constituted by such bit clock pulses constitute one setof data.

Among one set of data=100 bits, the 0th bit, the 9th bit, and those bitswhich are spaced from the 9th bit by successive 10 bits, i.e., the 19thbit, . . . , and the 99th bit serve as reference markers (P0˜P10) eachindicating a division of the time code. Each of the reference markers iscomposed of a greater amplitude corresponding to 8 cycles of the carriersignal and a smaller amplitude corresponding to 2 cycles of the carriersignal.

Between the reference markers, there are provided codes represented bynumerical values for "0.1 second", "second", "minute", "hour", and"day". These codes are represented by numerical values according to thebinary-coded decimal notation as described above. A binary value "0" isrepresented by a smaller amplitude corresponding to 2 cycles of thecarrier signal, and a binary value "1" is represented by a greateramplitude corresponding to 5 cycles of the carrier signal. The waveformof the carrier signal of the binary value "0" is illustrated in thelower portion of FIG. 1.

The code represented by a numerical value for "second" is formed by 8bits placed between the first reference marker P0 and the secondreference marker P1. Specifically, the 8 bits are used to indicatevalues of "1", "2", "4", "8", "10", "20", and "40", with one bit leftunassigned between "8" and "10". The numerical value for "second" of thetime code is expressed by the sum of the values of those bits which havethe binary value "1" represented by the waveform of the carrier signal.

Similarly, the code represented by a numerical value for "minute" isformed by 9 bits placed between the second reference marker P1 and thethird reference marker P2. Specifically, the 9 bits are used to indicatevalues of "1", "2", "4", "8", "10", "20", and "40", with one bit leftunassigned between "8" and "10". The last bit is left blank.

The code represented by a numerical value for "hour" is formed by 9 bitsplaced between the third reference marker P2 and the fourth referencemarker P3. Specifically, the 9 bits are used to indicate values of "1","2", "4", "8", "10", and "20", with one bit left unassigned between "8"and "10". The last two bits are left blank.

The code represented by a numerical value for "day" is formed by 9 bitsplaced between the fourth reference marker P3 and the fifth referencemarker P4 and 2 bits following the fifth reference marker P4.Specifically, these 11 bits are used to indicate values of "1", "2","4", "8", "10", "20", "40", "80", "100", and "200", with one bit leftunassigned between "8" and "10".

The code represented by a numerical value for "0.1 second" is formed by4 bits preceding the sixth reference marker P5. Specifically, the 4 bitsare used to indicate values of "0.1", "0.2", "0.4", and "0.8". The 3rd,4th and 5th bits from the fifth reference marker P4 are left blank.

A control function code for controlling operation of the data recorderin relation to the time code is assigned to 9×3=27 bits between thesixth reference marker P5 and the ninth reference marker P8. The controlfunction code is optionally used by the user of the data recorder, andhas no direct bearing on the present invention. Therefore, the controlfunction code is all indicated by "0", and will not be described indetail below.

A binary code of "2⁰ ", "2¹ ", "2² ", "2³ ", "2⁴ ", "2⁵ ", "2⁶ ", "2⁷ ","2⁸ ", "2⁹ ", "2¹⁰ ", "2¹¹ ", "2¹² ", "2¹³ ", "2¹⁴ ", "2¹⁵ ", "2¹⁶ ","2¹⁷ ", which is a straight binary representation of the above seconds,minutes, hours, and days, is formed by 18 bits between the ninthreference marker P8 and the final reference marker P10. The last bit isleft blank.

The above time code is generated repeatedly every 0.1 second. Each timethe time code is repeated, the code represented by a numerical value for"0.1 second", which is formed by the 4 bits preceding the sixthreference marker P5, is incremented by 0.1. The time code issuccessively formed so as to include values carried up to "second","minute", "hour", and "day".

In this manner, the time code of IRIG(A) is generated. A numerical valuerepresented by this time code indicates the timing of a starting end ofthe first reference marker P0. The time code of IRIG(A) indicates thetiming of 0.001 second with every successive bit clock pulse.

The time code shown in FIG. 1 signifies 173 days, 21 hours, 18 minutes,and 42.8 seconds. The position indicated by the arrow in FIG. 1signifies the timing of 173 days, 21 hours, 18 minutes, and 42.875seconds. With this time code, the cycles of the carrier signal may beused in time measurement for indicating the timing of 0.0001 second.

FIG. 2 of the accompanying drawings shows the time code of IRIG(B). InFIG. 2, the time code of IRIG(B) includes codes for "second", "minute","hour", and "day" which are represented by numerical values according tothe binary-coded decimal notation.

As shown in a lower portion of FIG. 2, the time code of IRIG(B) isgenerated by modulating a carrier signal of 1 kHz. A bit clock pulse isgenerated every 10 cycles of the carrier signal, i.e., every 0.01second. 100 bits constituted by such bit clock pulses constitute one setof data.

Among one set of data=100 bits, the 0th bit, the 9th bit, and those bitswhich are spaced from the 9th bit by successive 10 bits, i.e., the 19thbit, . . . , and the 99th bit serve as reference markers (P0˜P10) eachindicating a division of the time code. Each of the reference markers iscomposed of a greater amplitude corresponding to 8 cycles of the carriersignal and a smaller amplitude corresponding to 2 cycles of the carriersignal.

In relation to the reference markers, there are provided codesrepresented by numerical values for "second", "minute", "hour", and"day". These codes are represented by numerical values according to thebinary-coded decimal notation as described above. A binary value "0" isrepresented by a smaller amplitude corresponding to 2 cycles of thecarrier signal, and a binary value "1" is represented by a greateramplitude corresponding to 5 cycles of the carrier signal. The waveformof the carrier signal of the binary value "0" is illustrated in thelower portion of FIG. 2.

The code represented by a numerical value for "second" is formed by 8bits placed between the first reference marker P0 and the secondreference marker P1. Specifically, the 8 bits are used to indicatevalues of "1", "2", "4", "8", "10", "20", and "40", with one bit leftunassigned between "8", and "10". The numerical value for "second" ofthe time code is expressed by the sum of the values of those bits whichhave the binary value "1" represented by the waveform of the carriersignal.

Similarly, the code represented by a numerical value for "minute" isformed by 9 bits placed between the second reference marker P1 and thethird reference marker P2. Specifically, the 9 bits are used to indicatevalues of "1", "2", "4", "8", "10", "20", and "40", with one bit leftunassigned between "8" and "10". The last bit is left blank.

The code represented by a numerical value for "hour" is formed by 9 bitsplaced between the third reference marker P2 and the fourth referencemarker P3. Specifically, the 9 bits are used to indicate values of "1","2", "4", "8", "10", and "20", with one bit left unassigned between "8",and "10". The last two bits are left blank.

The code represented by a numerical value for "day" is formed by 9 bitsplaced between the fourth reference marker P3 and the fifth referencemarker P4 and 2 bits following the fifth reference marker P4.Specifically, these 11 bits are used to indicate values of "1", "2","4", "8", "10", "20", "40", "80", "100", and "200", with one bit leftunassigned between "8" and "10". The 3rd through 9th bits from the fifthreference marker P4 are left blank.

A control function code for controlling operation of the data recorderin relation to the time code is assigned to 9×3=27 bits between thesixth reference marker P5 and the ninth reference marker P8. The controlfunction code is optionally used by the user of the data recorder, andhas no direct bearing on the present invention. Therefore, the controlfunction code is all indicated by "0", and will not be described indetail below.

A binary code of "2⁰ ", "2¹ ", "2² ", "2³ ", "2⁴ ", "2⁵ ", "2⁶ ", "2⁷ ","2⁸ ", "2⁹ ", "2¹⁰ ", "2¹¹ ", "2¹² ", "2¹³ ", "2¹⁴ ", "2¹⁵ ", "2¹⁶ ","2¹⁷ ", which is a straight binary representation of the above seconds,minutes, hours, and days, is formed by 18 bits between the ninthreference marker P8 and the final reference marker P10. The last bit isleft blank.

The above time code is generated repeatedly every 1 second. Each timethe time code is repeated, the code represented by a numerical value for"second", which is formed by the 8 bits between the first referencemarker P0 and the second reference marker P1, is incremented by 1. Thetime code is successively formed so as to include values carried up to"minute", "hour", and "day".

In this manner, the time code of IRIG(B) is generated. A numerical valuerepresented by this time code indicates the timing of a start of thefirst reference marker P0. The time code of IRIG(B) indicates the timingof 0.01 second with every successive bit clock pulse.

The time code shown in FIG. 2 signifies 173 days, 21 hours, 18 minutes,and 42 seconds. The position indicated by the arrow in FIG. 2 signifiesthe timing of 173 days, 21 hours, 18 minutes, and 42.750 seconds. Withthis time code detected in an analog fashion, the cycles of the carriersignal may be used in time measurement for indicating the timing of0.001 second.

Heretofore, the time codes of IRIG(A), IRIG(B) have been successivelyrecorded on a single dedicated time code track assigned in aconventional so-called longitudinal multitrack data recorder. The timecodes and data to be handled are simultaneously recorded and reproducedby the data recorder. With the time code of IRIG(A), it is possible toobtain time information of the data in terms of the timing of 0.0001second. With the time code of IRIG(B), it is possible to obtain timeinformation of the data in terms of the timing of 0.001 second.

Even if a time code recorded on a longitudinal time code track at arecording rate is reproduced at a reproducing rate different from therecording rate, the time code can be read in synchronism with thereproducing rate. Therefore, the time information relative to recordeddata can be obtained even when the reproducing rate is varied. Therecorded time code can effectively be utilized when data recorded over along period of time are reproduced within a short period of time or whenthe time base of recorded data is expanded for a data analysis.

Data recorded with a time code may occasionally be required to be dubbedto produce a copy. When the data are recorded on multiple tracks, thereare created, in a strict sense, time differences between the tracks dueto the accuracy with which the head is mounted and other factors.Repeated data dubbing tends to cause the time code to suffer variationsthough the recorded data are not deteriorated as they are represented bydigital signals.

There has been developed a data recorder having a rotary head forrecording and reproducing data. Such a data recorder is highly analogousto an apparatus (VTR) for recording and reproducing a digital videosignal, for example. Such data recorder with a rotary head is capable ofrecording a very large amount of data of up to 770 Gbits on a 19 mm-widetape in a cassette of D-1 format, for example, which has beenestablished by SMPTE (Society of Motion Picture and TelevisionEngineers).

The data recorder of the type described above is also required toprovide accurate times of individual data that have been recordedthereby. Apparatus for recording and reproducing video signals, forexample, employ a time code prescribed by SMPTE. The time code of SMPTEis represented by encoded numerical values for hours, minutes, seconds,and frames of a video signal. The time code is recorded in relation toeach frame of the video signal to help the user search for and editdesired frames.

In the apparatus for recording and reproducing video signals, the videosignal has been recorded field by field, and it has been sufficient torecord the time code in relation to each frame of the video signal. Inthe data recorder, however, the time code recorded in relation to eachframe of the video signal is unable to determine correct times withsufficient accuracy.

In the case where the time codes of IRIG(A), IRIG(B) are applied to theabove data recorder for recording and reproducing by the rotary head, itmay be possible for the conventional data recorder to produce alongitudinal track recorded with a fixed head, for example, and record asuccession of time codes on the longitudinal track. With such anarrangement, time information can be obtained in terms of each ofoblique tracks recorded by the rotary head as with the SMPTE code.However, it is impossible to obtain in greater detail the timeinformation of individual data recorded on the oblique tracks.

The above problem manifests itself particularly if the fixed head andthe rotary head deviate from their proper relative positionalrelationship owing to an elongation or contraction of the recordingmedium. Specifically, when such a deviation is corrected (trackingcorrection), the reproduced data will be subjected to a variationcorresponding to a skew in the video signal, resulting in a loss of theassociation between the time code recorded on the longitudinal track andthe data recorded on the oblique tracks.

It has been proposed to provide areas for recording time codes inportions of oblique tracks that are recorded by the rotary head, andrecord the time codes in those areas with the same rotary head(transmission path) as used to record the data. According to such aproposal, the association between the time codes and the data is notlost, and it is possible to obtain correct time information of theindividual data.

With the above proposal, however, the areas for recording time codes arelimited to particular positions of certain tracks, for example. In orderto record successive time codes, as described above, in those particularpositions, a preceding time code, for example, is latched, and thelatched value is recorded. As a consequence, a time code at the timeassociated data are recorded is not correctly recorded.

It would be possible to adjust the data rate of input data and therecording data of a data recorder to bring a particular recordingposition into timed relation to a time code. However, such an adjustmentwould be highly complex to perform. Furthermore, it would not beentirely impossible to apply this adjustment process to a so-calledvariable-rate data recorder which buffers input data of any optionalrate and intermittently records the input data in synchronism with therecording rate inherent in the data recorder.

If the data recorder is used in combination with an apparatus whichemploys an existing time code, such as a time code of IRIG, then it isnecessary that the time code be successively read in the same manner aswith the conventional arrangement for recording the time code on thelongitudinal track.

SUMMARY OF THE INVENTION

The present invention has been made in view of the above drawbacks. Itis an object of the present invention to solve the problems associatedwith achieving strict timing conformity when a time code is recorded ina transmission path different from that of data, e.g., a multitrack or alongitudinal track with a rotary head, and when a time code cannotcorrectly be reproduced when the time code is recorded on the sametransmission path as data.

According to the present invention, there are provided means formultiplying a supplied time code to generate detailed time data, meansfor latching the time data at a given time in an input signal, and meansfor recording the latched time data on the same transmission path as theinput signal. With this arrangement, the supplied time code ismultiplied to generate detailed time data, the time data are latched ata given time in the input signal, and the latched time data are recordedon the same transmission path as the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrative of a time code of IRIG(A);

FIG. 2 is a diagram illustrative of a time code of IRIG(B);

FIG. 3 is an elevational view of a data recorder to which the presentinvention is applied;

FIG. 4 is a block diagram of the data recorder to which the presentinvention is applied;

FIG. 5 is a diagram illustrative of the data recorder;

FIG. 6 is a diagram illustrative of the data recorder;

FIG. 7 is a diagram illustrative of the data recorder;

FIG. 8 is a diagram illustrative of the data recorder;

FIG. 9 is a block diagram of a system which implements methods ofrecording and reproducing and apparatus for recording and reproducingtime codes according to the present invention;

FIGS. 10A and 10B are diagrams showing operation of the data recorder towhich the present invention is applied;

FIG. 11 is a diagram showing operation of the data recorder to which thepresent invention is applied;

FIGS. 12A through 12D are diagrams illustrative of another embodiment ofthe present invention; and

FIG. 13 is a diagram illustrative of a copying function of the datarecorder to which the present invention is applied.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Prior to a description of embodiments according to the presentinvention, there will be described below a so-called variable-rate datarecorder to which the present invention is applied and which buffersinput data (input signal) of any optional rate and intermittentlyrecords the input data in synchronism with the recording rate inherentin the data recorder.

A data recorder to which the present invention is applicable is designedaccording to standards (X3.175-1990) for an ID-1 format by ANSI(American National Standard Institute), for example. An overallarrangement of an apparatus which serves as such a data recorder isshown in FIG. 3.

In FIG. 3, serial or parallel input data of any optional rate from ameasuring device or the like are supplied to an interface device 100 forprocessing data to be recorded or reproduced by a data recorder havingan inherent recording rate. In the interface device 100, the suppliedinput data are buffered by a memory (not shown) or the like, and thebuffered data are read in synchronism with a recording rate inherent ina data recorder 200 which is substantially equivalent to a digital VTRof D-1 format, for example.

If the recording rate inherent in the data recorder 200 is high withrespect to the data rate of a variable-rate input, then the datarecorder 200 is switched into a recording mode when a certain amount ofinput data has been buffered depending on the storage capacity of thememory or the like, and the data recorder 200 is switched into a stopmode when almost all the buffered recording data have been read out. Theabove operation is repeated to intermittently record the input data ofany optional rate in timed relationship to the recording rate inherentin the data recorder 200.

For reproduction, data reproduced from the data recorder 200 arebuffered by the interface device 100, and the buffered output data areread in timed relationship to an optional rate of a data analyzer or thelike to which the interface device 100 is connected. If the reproducingrate inherent in the data recorder 200 is high with respect to the datarate of a variable-rate output, then the data are intermittentlyreproduced from the recorder 200, buffered in a memory, and read intimed relationship to an optional rate.

To the interface device 100, there is connected a control line forexchanging a control signal such as a recording or reproducing requestor information such as a data rate between itself and the measuringdevice, the data analyzer or the like which is connected, and alsobetween itself and the data recorder 200. A data line for inputting andoutputting accessory information (AUX data) to and from the datarecorder 200 is connected between the interface device 100 and the datarecorder 200. The apparatus which serves as the data recorder has theabove overall arrangement.

The interface device 100 for realizing a so-called variable-rate datarecorder which intermittently records input data of any optional rate intimed relationship to a recording rate inherent in the data recorder isshown by way of example in FIG. 4.

As shown in FIG. 4, a variable-rate data input (parallel) 101 which issupplied with parallel input data of any optional rate from a measuringdevice (not shown), for example, is connected to a multiplexer 102 forswitching between parallel and serial inputs. A variable-rate data input(serial) 103 which is supplied with serial input data of any optionalrate from the measuring device, for example, is connected to themultiplexer 102 through a serial-parallel converter 104. The multiplexer102 has an output connected to a variable-rate input FIFO memory 105which effects timing adjustment on the input data.

The variable-rate input FIFO memory 105 has an output connected to a busswitcher 106 for switching write and read data buses of a built-inmemory for buffering data. The bus switcher 106 is connected to a DRAM107 which serves as the built-in memory. The DRAM 107 has an outputconnected through the bus switcher 106 to a recorder output FIFO memory108 which effects timing adjustment on recording data. The output FIFOmemory 108 has an output connected to a data output 109 for outputtingrecording data at an inherent rate to the data recorder 200 (not shown).

A data input 110 which is supplied with reproduced data from the datarecorder 200 is connected to an input FIFO memory 111 which effectstiming adjustment on the reproduced data. The input FIFO memory 111 hasan output connected through the bus switcher 106 to the DRAM 107. Theoutput of the DRAM 107 is connected through the bus switcher 106 to avariable-rate input FIFO memory 112 which effects timing adjustment onoutput data.

The FIFO memory 112 has an output connected to a variable-rate dataoutput (parallel) 113 which outputs parallel output data at an optionalrate to a data analyzer (not shown), for example. The output of the FIFOmemory 112 is connected to the serial-parallel converter 104. Theserial-parallel converter 104 is capable of converting the input datafrom serial to parallel form and also converting the output data fromparallel to serial form. In this case, the serial-parallel converter 104converts parallel data to serial data. The serial-parallel converter 104has an output connected to a variable-rate data output (serial) 114which outputs serial output data at an optional rate to the dataanalyzer (not shown), for example.

An output clock signal is selected depending on switching between theinputs. For selecting a desired interpolation clock signal, aninterpolation clock generator 115 which generates such an interpolationclock signal is connected to the serial-parallel converter 104. To a busline 119, there is connected a DMA controller 121 for controlling datatransfer between the DRAM 107 and the FIFO memories 105, 108, 111, 112depending on a mode.

An input/output unit (for example, RS232C/GP-IB (IEEE-488) interface)116 for inputting and outputting control data such as data rateinformation from the measuring device, the data analyzer, or the like isconnected to an I/O port 117 which controls the inputting and outputtingof data. An input/output unit 118 for inputting and outputting controldata such as operation data of the data recorder 200 is connected to theI/O port 117. The I/O port 117 is connected through the bus line 119 toa CPU 120.

To the data input 110, there is connected an input of a reproducedheader FIFO memory 129 for extracting header information from reproduceddata that are obtained by a reproducing operation immediately prior tothe start of a recording operation, for the operation of the datarecorder 200. The reproduced header FIFO memory 129 has an outputconnected to the bus line 119.

A time code interface 127 for achieving recording and reproduction oftime codes is connected through the bus line 119 to the CPU 120. A timecode input 126 and a time code output 128 are connected to the time codeinterface 127.

In the interface device 100, an input of an output header FIFO memory124 is connected through the bus line 119 to the CPU 120, and an outputof the output header FIFO memory 124 is connected to the output of FIFOmemory 112. The output of the multiplexer 102 is connected to an inputof an input header FIFO memory 122, whose output is connected throughthe bus line 119 to the CPU 120.

The output header FIFO memory 124 and the input header FIFO memory 122are used to perform a copying function of the interface device 100 (afunction to copy (dub) the reproduced data from the data recorder 200 ona tape in another data recorder). The copying function will be describedlater on.

Operation of the interface device 100 of the above structure will bedescribed below. Prior to a description of the operation of theinterface device 100, however, a recording format of the data recorder200 connected to the interface device 100 will first be described below.

FIG. 5 shows a recording pattern produced by the data recorder 200.

The data recorder 200 records and reproduces data on one unit of fouroblique tracks (referred to as a 1 track set). Header information ofdata recorded in a 1 track set is recorded in a hatched portion at therecording start of a first track of the 1 track set.

FIG. 6 shows a data structure of the 1 track set.

The data of the 1 track set are composed of the header information,described above, of 128 bytes and data of 144,304 bytes, for a total of144,432 bytes.

The header information of 128 bytes is constructed as shown in FIG. 7.As shown in FIG. 7, the first 5 bytes serve as a header ID sectioncomposed of 2 bytes of data "00" and ID data of 3 bytes representing the1 track set. The next 8 bytes serve as a control flag section composedof a write/retry flag of 1 byte, an effective data count value of 3bytes, an error count value of 1 byte, etc. The next 3 bytes serve as atrack set ID section which are the same as those of the ID datarepresenting the position information of the 1 track set on the tape.

The next 6 bytes serve as a time code data section composed of 27-bitdata of seconds, minutes, hours, and days which are represented by atime code of IRIG, for example, as converted into a straight binaryrepresentation, and 21-bit fractional data (described later on). Thenext 4 bytes serve as a user data section related to the time code, andrecord a 27-bit control function code contained in a time code of IRIG,for example. The next 32 bytes serve as an extended user data section.The remaining 70 bytes serve as a history area for recording informationcomposed of time and position information which will be used to effect atime code search, as described later on.

The operation of the interface device 100 according to the presentinvention will be described below with reference to FIG. 4.

Input data from the variable-rate data input (parallel) 101 or thevariable-rate data input (serial) 103 which is selected by themultiplexer 102 are supplied to the variable-rate input FIFO memory 105,controlled in timing by the variable-rate input FIFO memory 105 forwriting, and then written into the DRAM 107 through the bus switcher106.

As described later on, the interface device 100 has a frequency dividerfor counting data clock pulses corresponding to the input data by144,302. The timing of the input data of 144,304 bytes to be recorded ina 1 track set is detected by an output signal (data sync) from thefrequency divider.

The DRAM 107 has addresses as shown in FIG. 8. Numbers on the left-handside indicate addresses, each formed of 1 byte. Addresses 128˜144,432(corresponding to 144,304 bytes), shown hatched in FIG. 8, serve as aregion for storing data, and addresses 0˜127 serve as a region forstoring header information.

Therefore, input data composed of every 144,304 bytes are stored in theaddresses 128˜144,432 of the DRAM 107.

At this time, the CPU 120 generates header information of 128 bytesdepending on the data sync, referred to above. Time code data of theheader information are provided as follows:

A time code of IRIG(A) or IRIG(B), described above, which has beensupplied to the time code input 126 is sent to the time code interface127.

The time code interface 127 and the CPU 120 processes the supplied timecode of IRIG to generate 27-bit data which are represented by thesupplied time code of IRIG as converted into a straight binaryrepresentation, and 21-bit fractional data.

The operation of the time code interface 127 will be described in detaillater on with reference to FIG. 9.

The time code data generated by the time code interface 127 are readthrough the bus line 119 by the CPU 120, and inserted into the time codedata section in the header information.

The header information thus generated by the CPU 120 is written intoaddresses 0˜127 of the DRAM 107 through the bus line 119, a header VRAM123, and the bus switcher 106.

The header information and the input data that have been written in theDRAM 107 are successively read out, and sent through the recorder outputFIFO memory 108 to the data output 109. From the data output 109, theheader information and the input data are supplied as data recorderoutput data compatible with the recording rate inherent in the datarecorder 200 to the data recorder 200, and recorded thereby.

When the data recorder 200 is played back, reproduced data supplied tothe data input 110 are delivered through the input FIFO memory 111 andthe bus switcher 106 to the DRAM 107, in which the header information iswritten in addresses 0˜127 and the data in addresses 128˜144,432.

The data in the reproduced data written in the DRAM 107 are outputtedthrough the bus switcher 106 and the variable-rate input FIFO memory 112from the variable-rate data output (parallel) 113 or the variable-ratedata output (serial) 114 at a data rate as requested by the dataanalyzer (not shown) or the like.

The header information written in the DRAM 107 is read through the busswitcher 106 and the header VRAM 123 by the CPU 120.

The time code data, which are composed of the 27-bit data of seconds,minutes, hours, and days which are represented by a straight binaryrepresentation, and the 21-bit fractional data, in the headerinformation read by the CPU 120 are processed, and thereafter sentthrough the bus line 119 to the time code interface 127. In the timecode interface 127, the original time code of IRIG is restored from thetime code data, and outputted from the time code output 128 inassociation with the data output.

The FIFO memories 105, 108, 111, 112 are used to simultaneously writedata into and read data from the DRAM 107. Specifically, to output therecording data for the data recorder 200 while input data from themeasuring device (not shown), for example, are being inputted, at thesame time that the input data are being written into the FIFO memory105, the data of the DRAM 107 are written into the FIFO memory 108 at ahigh speed by the DRAM controller 121 so that the data remain filled atall times. Thereafter, the recording data written in the FIFO memory 108are read at the rate inherent in the data recorder 200, and the inputdata written in the FIFO memory 105 are all read out and written intothe DRAM 107.

To output the output data for the data analyzer (not shown) while thereproduced data from the data recorder 200 are being written, at thesame time that the reproduced data are being written into the FIFOmemory 111, the data of the DRAM 107 are written into the FIFO memory112 at a high speed by the DRAM controller 121 so that the data remainfilled at all times. Thereafter, the recording data written in the FIFOmemory 112 are read at an optional rate, and the reproduced data writtenin the FIFO memory 111 are all read out and written into the DRAM 107.In this manner, it is possible to simultaneously write data into andread data from the DRAM 107.

An embodiment of methods of recording and reproducing and apparatus forrecording and reproducing time codes according to the present inventionwill be described in detail below.

FIG. 9 shows in detail an arrangement of the time code interface 127shown in FIG. 4 which carries out the present invention. The arrangementshown in FIG. 9 generates time code data from a time code of IRIG andrestores the time code of IRIG from the time code data, as follows:

In the generation of the time code data, the 27-bit data of seconds,minutes, hours, and days are indicated by a straight binaryrepresentation converted from:

3-figure day data!×24×60×60

+ 2-figure hour data!×60×60

+ 2-figure minute data!×60

+ 2-figure second data!

in the time code of IRIG supplied to the time code input 126.

In FIG. 9, for recording the time code, a signal from a time code input1 (126) is supplied through a level control circuit 2 which adjusts thelevel of the signal, to a data extractor 3 which determines a smalleramplitude corresponding to 2 cycles of the carrier signal and a greateramplitude corresponding to 5 cycles thereof and extracts binary values"0" and "1". The data from the data extractor 3 are written through aserial-parallel converter 6 into a memory 7, and the data written in thememory 7 are supplied to a CPU 8, which corresponds to the CPU 120. TheCPU 8 calculates the 27-bit data of seconds, minutes, hours, and days.

The CPU 8 determines 4-bit data prior to the sixth reference marker P5in data written in the memory 7. If all the 4 bits of the 4-bit data are"0", then the CPU 8 determines that the inputted time code is a timecode of IRIG(B). If the 4 bits of the 4-bit data contain a value, thenthe CPU 8 determines that the inputted time code is a time code ofIRIG(A).

The signal from the level control circuit 2 is supplied to a bit clockdetector 4 for detecting a bit clock pulse per data of "0" or "1". Thebit clock detector 4 detects bit clock pulses in the time code. Thesignal from the level control circuit 2 is also supplied to asynchronization detector 5 for detecting when two reference markerscomposed respectively of a greater amplitude corresponding to 8 cyclesof the carrier signal and a smaller amplitude corresponding to 2 cyclesthereof are successively generated. The synchronization detector 5detects a synchronizing signal in the time code.

The synchronizing signal detected by the synchronization detector 5 issupplied to a frequency detector 9 for detecting the frequency of thecarrier signal of the inputted time code. The synchronizing signal fromthe synchronization detector 5 and the bit clock pulses from the bitclock detector 4 are supplied to an input detector 10 for detectingwhether there is an inputted time code or not. Detected signals from thefrequency detector 9 and the input detector 10 are supplied to the CPU8, which generates a control signal for controlling the frequency andphase of a clock signal that is generated by a clock generator 11 whichgenerates an internal operation clock signal.

Specifically, the frequency detector 9, the input detector 10, and theclock generator 11 are operated in the same manner as a phase-lockedloop through the CPU 8, and are synchronized with the bit clock pulsesof the inputted time code for generating a clock signal of a certainfrequency which is a multiple of the frequency of the bit clock pulses.The frequency of the clock signal which is generated is 640 kHz witherrors corrected if the inputted time code is a time code of IRIG(A),and 512 kHz with errors corrected if the inputted time code is a timecode of IRIG(B).

The clock signal is supplied to a counter 12 which comprises a modulo-64or -512 counter a, a modulo-10 counter b, and a counter c. The signalfrom the synchronization detector 5 is supplied to a load pulse selector13 which selects load pulses when data are recorded and reproduced. Theload pulse selector 13 is controlled by the control signal from the CPU8. When data are recorded, the synchronizing signal of the time codefrom the synchronization detector 5 is selected, and supplied as a resetpulse to the counter 12.

When the inputted time code is a time code of IRIG(A), the counter aoperates as a modulo-64 counter and directly counts clock pulses, andoutputs a carry each time it counts 64 clock pulses. The carry outputtedfrom the counter a is counted by the counter b, which outputs a carryeach time it counts 10 carries from the counter a. The carry outputtedfrom the counter b is counted by the counter c. The counters a, b arereset by the signal from the bit clock detector 4.

The counter c counts a frequency-divided clock signal of 1 kHz, andoutputs 7-bit numerical values in the positions of 0.01 second and 0.001second. The counter b counts a frequency-divided clock signal of 10 kHz,and outputs a 4-bit numerical value in the position of 0.0001 second.The counter a counts a value representing the time when thefrequency-divided clock signal of 10 kHz (which is the same as thecarrier signal) is divided into 64 equal portions, and outputs a 6-bitvalue indicating that time.

When the inputted time code is a time code of IRIG(B), the counter aoperates as a modulo-512 counter and directly counts clock pulses, andoutputs a carry each time it counts 512 clock pulses. The carryoutputted from the counter a is counted by the counter b, which outputsa carry each time it counts 10 carries from the counter a. The carryoutputted from the counter b is counted by the counter c. The counters aand b are reset by the signal from the bit clock detector 4.

The counter c counts a frequency-divided clock signal of 0.1 kHz, andoutputs 7-bit numerical values in the positions of 0.1 second and 0.01second. The counter b counts a frequency-divided clock signal of 1 kHz,and outputs a 4-bit numerical value in the position of 0.001 second. Thecounter a counts a value representing the time when thefrequency-divided clock signal of 1 kHz (which is the same as thecarrier signal) is divided into 512 equal portions, and outputs a 10-bitvalue indicating that time.

The count from the counter 12 is supplied to a latch 14 for latchingdata according to a latch pulse, described later. A signal correspondingto a signal which is produced when the frequency of the bit clock pulsesof the inputted time code is divided by 100 is outputted as the carrieroutput from the counter b, and supplied as a shift clock signal to theserial-parallel converter 6.

The clock signal of the data (input signal) from the measuring device(not shown) is supplied to a data clock input 15. The clock signal fromthe data clock input 15 is supplied to a frequency divider 16, whichdivides the frequency of the clock signal into a 1/144,304 frequency.Therefore, the frequency divider 16 outputs a frequency-divided signal(referred to as a data sync signal) each time it counts 144,304 dataclock pulses, and the data sync signal is supplied through a latch pulsegenerator 17 to the latch 14.

The latch 14 latches the count from the counter 12 in timed relationshipto data next to the data (input data) supplied from the measuring device(not shown) and composed of 144,304 bytes recorded in a 1 track set, andlatches a fractional value of the time code at the time of the firstdata recorded in the 1 track set.

The value latched by the latch 14 is supplied to the CPU 8, and the datasync signal from the frequency divider 16 is supplied to the CPU 8. Thevalue supplied to the CPU 8 is converted into a straight binary value,generating 21-bit fractional data in the time code data.

When the inputted time code is a time code of IRIG(A), the 21-bitfractional data in the time code data are of a straight binaryrepresentation converted from:

( data of 0.1 second of the time code of IRIG!/10

+ value of the counter c!/10/100

+ value of the counter b!/10/100/10

+ value of the counter a!/10/100/10/64)

×2097152 (=2²¹).

When the inputted time code is a time code of IRIG(B), the 21-bitfractional data in the time code data are of a straight binaryrepresentation converted from:

( value of the counter c!/100

+ value of the counter b!/100/10

+ value of the counter a!/100/10/512)

×2097152.

In this manner, the 27-bit data of seconds, minutes, hours, and days,and the 21-bit fractional data in the time code data are generated, andthe time code data in the header information are generated using thosedata.

In the methods of recording and reproducing and apparatus for recordingand reproducing time codes according to the present invention, thesupplied time code is multiplied to generate detailed time data, thetime data are latched at a given time in the input signal, the latchedtime data are converted into a given data format, and the converted timedata are recorded in the same transmission path as the input signal. Inthis manner, the correct time data can be recorded in the sametransmission path as the input signal, and the time of recordedindividual data can accurately be determined.

The time code is recorded per data of 1 track set supplied from themeasuring device, for example, and recorded per given amount of supplieddata irrespective of the rate of the supplied data. Therefore, the abovedetailed time code can be recorded by a data recorder having anyoptional variable rate.

For reproducing the detailed time code that has been recorded, areproducing data clock signal from the data analyzer (not shown) issupplied to the data clock input 15. The data clock signal from the dataclock input 15 is supplied to the frequency divider 16, which dividesthe frequency of the data clock signal into a 1/144,304 frequency togenerate a data sync signal per 1 track set. The data sync signal isthen supplied to a frequency detector 21 for detecting a data syncsignal frequency.

A detected signal from the frequency detector 21 is supplied to the CPU8. The CPU 8 calculates time intervals upon recording between data syncsignals from the reproduced time code, and calculates a time ratiobetween the data sync signals at the time when they are recorded andreproduced. The time ratio is supplied to the clock generator 11, whichgenerates a reproduction clock signal as corrected by a ratio betweenrecording and reproducing speeds.

The fractional value in the reproduced time code is inversely convertedinto the values of the counters a, b, c by the CPU 8, and they arelatched by a latch 23. The latched values are then supplied to loadterminals of the counter 12. The data sync signal from the frequencydivider 16 is supplied to the load pulse selector 13. For reproduction,the supplied data sync signal is selected, and supplied as load pulsesto the counter 12. After the fractional value of the reproduced timecode is loaded, the counter 12 counts the reproduced clock signal.

The 27-bit values of seconds, minutes, hours, and days in the reproducedtime code are inversely converted into data representing 3-figure days!,2-figure hours!, 2-figure minutes!, 2-figure seconds!, and 0.1 second!of IRIG(A), for example, by the CPU 8, and the converted data aresupplied to the memory 7. The data stored in the memory 7 are thensupplied through a parallel-serial converter 24 to a time code generator25 for generating the time code of IRIG(A).

A time code generated by the time code generator 25 is supplied to a ROM26 in which generated data of sine wave are written, and the ROM 26 issupplied with the value of the counter a from the counter 12. Thegenerated time code is thus converted into a time code represented by acarrier signal of sign wave as amplitude-modulated which has beenestablished by the IRIG.

In the ROM 26, there are written generated data corresponding to thelevels at times when one period of a sign wave, for example, is dividedinto 64 equal portions. If the time code is a time code of IRIG(A), thenthe generated data are read according to the value of the counter a fromthe counter 12. If the time code is a time code of IRIG(B), then thegenerated data are read according to a high-order 6-bit value of thecounter a. The generated data represent data of greater amplitudes,smaller amplitudes, and transitional conditions upon switching betweenthe greater and smaller amplitudes. Necessary data are read outaccording to the time code from the time code generator 25.

The ROM 26 produces a signal of the generated time code represented by acarrier signal of sign wave as amplitude-modulated which has beenestablished by the IRIG. This signal is supplied to a D/A converter 27,and the signal from the CPU 8 is also supplied to the D/A converter 27through a gain control circuit 28 for varying the output level. The D/Aconverter 27 supplies a converted signal to a time code output 29 (128).

In the methods of recording and reproducing and apparatus for recordingand reproducing time codes according to the present invention, thedifferences between successively reproduced time data and reproducedtime intervals are measured, a reproduced clock signal is controlledbased on the ratio between the measured differences and time intervals,the time data are preset in the counter, and the controlled reproducedclock signal is supplied to the counter to produce the count of thecounter as a reproduced time code. In this manner, time codesrepresenting times at which an input signal is recorded at an optionalrate can successively be reproduced.

According to the present invention, furthermore, a portion of thedetailed time data includes information having a generatable resolutionof a prescribed carrier signal of the supplied time code, theinformation representing divisions of the carrier signal, so that thetime code can be reproduced with high accuracy.

More specifically, in the methods of recording and reproducing andapparatus for recording and reproducing time codes according to thepresent invention, successively generated time codes are intermittentlyrecorded at optional times in timed relationship to the data, and therecorded time codes are successively reproduced. In this manner, therecorded times can accurately be obtained, and correct recorded timescan be reproduced with respect to any optional recording rate. Correctrecorded times with respect to data between intermittently recorded timecodes can also be obtained.

By controlling reproduced clock signals of the reproduced time codesdepending on the ratio between the differences between successivelyreproduced time data and reproduced time intervals, time codes areproduced in synchronism with a reproducing speed even if the reproducingspeed is different from a recording speed. These time codes can beutilized when data recorded over a long period of time are reproduced ina short period of time or when the time base of recorded data isexpanded for a data analysis.

In the methods of recording and reproducing and apparatus for recordingand reproducing time codes according to the present invention,furthermore, time codes can effectively utilized in a so-calledvariable-rate data recorder which intermittently records input data ofany optional rate at a recording rate inherent in the data recorder.

Specifically, the variable-rate data recorder buffers input data of anyoptional rate and intermittently records the input data in synchronismwith the recording rate inherent in the data recorder. Therefore, thetime at which the data are recorded in the data recorder does notcorrespond to the time at which the input data are inputted. Accordingto the conventional process by which time codes are recorded at the sametime input data are recorded, the time codes cannot accurately berecorded.

In the methods of recording and reproducing and apparatus for recordingand reproducing time codes according to the present invention, a timecode representing the time when first input data of each track set areinputted is recorded in detail in header information of the track set,and successive time codes are generated by multiplying the time code ofeach track set. In this fashion, correct time codes can be recorded andreproduced by the data recorder which intermittently records the data.

In the methods of recording and reproducing and apparatus for recordingand reproducing time codes according to the present invention, data arenormally recorded and reproduced by the data recorder 200 as shown inFIGS. 10A and 10B, for example. In FIGS. 10A and 10B, the left-hand sizeindicates a start of the tape, and the right-hand side indicates an endof the tape.

FIG. 10A is illustrative of operation of the data recorder 200 when itreproduces data. In FIG. 10A, a desired reproduction starting point issearched for in a preroll mode. When the reproduction starting point isdetected, synchronizing operation is started from a point where thepreroll mode has been effected, and a first reproduction mode (FWD1) iscarried out from the reproduction starting point. When the firstreproduction mode (FWD1) is finished, the data recorder 200 enters astop mode. Thereafter, synchronizing operation is resumed from a pointwhere a preroll mode has been effected, and a second reproduction mode(FWD2) is carried out from a point where the first reproduction mode(FWD1) is finished. The above process is repeated to reproduce data in athird reproduction mode (FWD3) and so on.

FIG. 10B is illustrative of operation of the data recorder 200 when itrecords data. In FIG. 10B, when the start or beginning of the tape (BOT)is detected in a rewinding (REW) mode, a given tape start format(REC-FB) is first recorded. When a start of a data recording region isdetected, the data recorder 200 enters a stop mode. Thereafter, asynchronizing operation is resumed from a point where a preroll mode hasbeen effected, and a first recording mode (REC1) is carried out from thestart of the data recording region. When the first recording mode (REC1)is finished, the data recorder 200 enters a stop mode. Thereafter, thesynchronizing operation is resumed from a point where a preroll mode hasbeen effected, and a second recording mode (REC2) is carried out from apoint where the first recording mode (REC1) is finished. The aboveprocess is repeated to reproduce data in a third reproduction mode(REC3) and so on.

In this manner, the data recorder 200 effects normal recording andreproducing operations. Since the data recorder 200 intermittentlyoperates as described above, it can smooth record and reproduce datawhich have been intermittently processed by a host computer or whichhave any optional variable rate different from the recording rate of thedata recorder.

FIG. 11 is illustrative of operation of the data recorder 200 when itreproduces data in a reverse mode. In FIG. 11, a desired reproductionstarting point is searched for in a preroll mode. The synchronizingoperation is started from a point where the preroll mode has beeneffected prior to the reproduction starting point, and a firstreproduction mode (FWD1) is carried out from the reproduction startingpoint. When the first reproduction mode (FWD1) is finished, the datarecorder 200 enters a stop mode. If data are to be reproduced in areverse mode at this time, then the reproduced data written in the DRAM107 are read in an order opposite to the order in which they have beenrecorded, and the CPU 8 processes time code data in a reverse order.

Thereafter, a desired reproduction starting point preceding the firstreproduction mode (FWD1) is searched for in a preroll mode, and thesynchronizing operation is started from a point where the preroll modehas been effected prior to the reproduction starting point. A secondreproduction mode (FWD1) is carried out from the reproduction startingpoint. When the second reproduction mode (FWD2) is finished, the datarecorder 200 enters a stop mode. The above process is repeated toreproduce data in a third reproduction mode (FWD3) and so on. Thereverse mode is carried out in the manner described above.

In the methods of recording and reproducing and apparatus for recordingand reproducing time codes according to the present invention, the70-byte history area in the header information is used to keep historyinformation which represents blocks of data each recorded successivelyfrom the start to end of each recording event. Using such historyinformation, any recorded data can be searched for quickly by indicatingtime.

Specifically, the present invention is typically applied to a system forrecording data observed by an artificial satellite. In such a system,one recording event is carried out at 60 Mbps for 15 to 20 minutes, andabout six recording events take place a day. In the system, about 10˜15blocks of data are recorded in a large-size tape cassette. It isrequested to search for such recorded data using time codes describedabove.

As shown in FIGS. 12A through 12D, 60 bytes out of the 70 bytes of thehistory area are used to record a track set ID (3 bytes) and a time code(3 bytes) as position information of a start of each of the blocks.Using the 60 bytes allows ten sets of recording information composed oftime and position information to be recorded, forming a history of therecorded information. A unit of up to 2 seconds can be recorded using 3bytes for time codes.

In this manner, a history area of recorded information including timedata (time codes) of starts of successively recorded input signals andposition information (track set IDs) on the recording medium is providedon a data format (header). To update the history area, as shown in FIG.4, the data input 110 supplies reproduced data to the bus line 119through the reproduced header FIFO memory 129 for extracting headerinformation from reproduced data.

At the time data starts being recorded, a preceding track set isreproduced during synchronizing information prior to the recordingoperation. Header information of the track set is then extracted by theFIFO memory 129, and supplied through the bus line 119 to the CPU 8.Based on the history of the extracted old recorded information, a newhistory is generated, and inserted into header information to berecorded.

The data of the history are successively recorded in FIFO order as shownin FIGS. 12A, 12B, 12C. When more than ten sets of data are introduced,the oldest set of data is removed as shown in FIG. 12D, so that latestten sets of data are recorded at all times. If desired data are searchedfor from the end of the recorded data, then the data of the historyrecorded at the end block are reproduced to obtain position informationof the tape, and it is predicted which block contains a desired time forthereby quickly searching for the desired data.

When an optional time (time code) is indicated by the data analyzer, thedata of the history of the recorded information are reproduced, and theindicated time is converted into a track set ID to search for thecorresponding data.

To search for data using an indicated time code, usually, two or moretrack sets are reproduced at the position, and the difference (ΔTC)between the time codes of the track sets and the difference (ΔID)between track set IDS of the track sets are calculated from the headerinformation of the reproduced track sets. From these two differences,and the time codes and the track set IDs at those positions, a track setID is calculated which corresponds to the indicated time code, and thecalculated track set ID is searched for.

If the position of the track set ID calculated from the time codelargely exceeds the end of the tape, then the tape is played back at aposition divided according to a ratio at which the time code largelyexceeds the end of the tape or at a central position of the tape, thehistory of the recorded information is read at that position, and atrack set ID corresponding to the indicated time code is corrected basedon the read history of the recorded information and searched for.

If a recording end point on the tape is detected based on whether thereare ID data recorded in a control track, for example, while theindicated time code is being searched for, then the tape is played backfrom a header preceding the recording end point, the history of therecorded information in the header information is read, and a track setID corresponding to the indicated time code is corrected based on theread history of the recorded information and searched for. The positionof the track set ID corresponding to the indicated time can thus besearched for using the data of the history of the recorded information.

The first time a tape to be recorded and reproduced is loaded, the dataof the history of the recorded information may successively bereproduced in a normal playback or searching mode, and, using thereproduced data, an association table of all time codes and track setIDs of the tape may be produced in a memory in the CPU 120. With thetable thus produced, the searching mode can be carried out at a higherspeed using the data of the table until the tape is ejected.

Since the history of recorded information including time data of thestarts of recorded blocks and position information thereof on therecording medium is provided in a given data format, data can besearched for at a high speed using time codes when they are reproduced.

In the above embodiment, the recording rate is uniform on one tape, andhence the history of recorded information is composed of time data ofthe starts of recorded blocks and position information thereof. However,if time data of the ends of recorded blocks and position informationthereof are recorded as pairs, then the methods and apparatus accordingto the present invention can handle different recording rates of theblocks.

In the above apparatus, the time codes may be recorded in and reproducedfrom areas other than the header area described above. For example, in adigital tape recorder according to standards (X3.175-1990) for an ID-1format by ANSI, the data area of accessory information in a preamble ineach track is of 54 bits, allowing 24 bytes of accessory information(AUX data) to be used in 1 track set. Therefore, the above detailed timecodes can be recorded in and reproduced from the data area.

With such an arrangement, the control CPU 120 is bidirectionallyconnected to the data recorder through an accessory informationinput/output unit 125. Since the time codes are recorded and reproducedseparately from the data in the data area, the frequency divider 16shown in FIG. 9 divides the frequency into a 1/144,432 frequency. Inthis fashion, the detailed time codes can be recorded in and reproducedfrom the data area of accessory information in a preamble in every 4tracks.

A copying function of the interface device 100 will be described below.

The reproduced data from the data recorder 200 are supplied through thedata input 110, the input FIFO memory 111, and the bus switcher 106 tothe DRAM 107.

The input/output unit 118 is supplied with ID data (data indicative ofabsolute addresses of a tape recorded in the control track) of thecontrol track reproduced by the data recorder 200. The accessoryinformation input/output unit 125 is supplied with accessory information(AUX data) reproduced by the data recorder 200. The supplied ID data andaccessory information (AUX data) are supplied to the CPU 120 through theI/O port 117 and the bus line 119.

Based on the supplied ID data and accessory information (AUX data), theCPU 120 generates a copy header composed of a total of 20 bytes, which,as shown in FIG. 13, include 3 bytes of ID data, 12 bytes of accessoryinformation (AUX data), and 5 bytes of reserved data successivelyarranged from the beginning of the data. The copy header is positionedat the beginning of the data in each unit of 144,432 bytes of data whichare recorded and reproduced. The copy header is generated only when thecopying function is performed.

When 144,432 bytes of data can be outputted from the DRAM 107, the copyheader generated by the CPU 120 is outputted to the variable-rate dataoutput (parallel) 113 through the output header FIFO memory 124 or tothe variable-rate data output (serial) 114 through the serial-parallelconverter 104.

Following the outputting of the copy header, 144,432 bytes of data(including time code data as described later on, which however are notprocessed, but handled as simple data when the copying operation isperformed) from the DRAM 107 are supplied to the variable-rate dataoutput (parallel) 113 through the variable-rate input FIFO memory 112 orto the variable-rate data output (serial) 114 through theserial-parallel converter 104.

The copy header and the following 144,432 bytes of data are combinedwith each other and sent to the data recorder.

While the copying function is being performed by the interface device100, in order to add a copy header to data, the transfer rate foroutputting data from the DRAM 107 to the variable-rate data output(parallel) 113 or the variable-rate data output (serial) 114 is madehigher than the rate of the reproduced data from the data recorder 200by about 0.05% corresponding to the added copy header.

Operation of a copying data recorder will be described. The copying datarecorder is of the same structure as the reproducing data recorder, andwill be described below with reference to FIG. 4.

When the copying function is performed, since it is already known that acopy header is positioned in 20 bytes at the beginning of the input datasupplied to the interface device 100, the data of 20 bytes at thebeginning of the input data from the variable-rate data input (parallel)101 or the variable-rate data input (serial) 103 are introduced as acopy header through the input header FIFO memory 122 into the CPU 120.

144,432 bytes of data inputted following the copy header are writtenthrough the variable-rate input FIFO memory 105 and the bus switcher 106into the DRAM 107. The written data are buffered for a certain period oftime by the DRAM 107, and thereafter read therefrom and sent through therecorder output FIFO memory 108 and the data output 109 to the datarecorder, in which the data are recorded on a tape. In this manner, thedata are copied.

ID data of 3 bytes in the copy header introduced into the CPU 120 aredelayed for the same period of time as the data are buffered by the DRAM107, and thereafter sent through the I/O port 117 and the input/outputunit 118 to the data recorder. In the data recorder, the supplied IDdata are loaded into an ID data generator (not shown), which equalizesthe ID data of the destination tape with the ID data of the source tape.In this manner, the copying of the ID data is achieved.

Accessory information (AUX data) of 12 bytes in the copy headerintroduced into the CPU 120 are delayed for the same period of time asthe data are buffered by the DRAM 107, and thereafter sent through theI/O port 117 and the accessory information input/output unit 125 to thedata recorder. In the data recorder, the necessary accessory informationis recorded in a given recording region on the tape. In this manner, thecopying of the Accessory information (AUX data) is achieved.

According to the copying function of the interface device 100, asdescribed above, data and accessory information (AUX data) canefficiently be copied through a single transmission path whichinterconnects either the variable-rate data output (parallel) 113 of thesource and the variable-rate data input (parallel) 101 of thedestination or the variable-rate data output (serial) 114 and thevariable-rate data input (serial) 103.

In the copying operation, time codes are recorded and reproduced basedon time code data that are generated according to the present inventionas described above. Therefore, the time codes will not be varied withrespect to the data even if the copying operation is repeated.

According to the present invention, the supplied time code is multipliedto generate detailed time data, the time data are latched at a giventime in the input signal, the latched time data are converted into agiven data format, and the converted time data are recorded in the sametransmission path as the input signal. In this manner, the correct timedata can be recorded in the same transmission path as the input signal,and the time of recorded individual data can accurately be determined.

Further according to the present invention, the differences betweensuccessively reproduced time data and reproduced time intervals aremeasured, a reproduced clock signal is controlled based on the ratiobetween the measured differences and time intervals, the time data arepreset in the counter, and the controlled reproduced clock signal issupplied to the counter to produce the count of the counter as areproduced time code. In this manner, time codes representing times atwhich an input signal is recorded at an optional rate can successivelybe reproduced.

I claim:
 1. A method of recording a time code, comprising the stepsof:multiplying a supplied time code to produce a product, therebygenerating detailed time data; latching the detailed time data at agiven time in a data input signal; converting the latched time data intoconverted time data having a given data format; and recording theconverted time data in a same transmission path as the data inputsignal.
 2. A method according to claim 1, wherein said detailed timedata include in a portion thereof information representing divisions ofa prescribed carrier signal of the supplied time code.
 3. A methodaccording to claim 1, wherein said given data format includes a historyof recorded information including the time data at a beginning of theinput signal which is successively recorded and position informationthereof on a recording medium.
 4. A method of reproducing a time code,comprising the steps of:multiplying a supplied time code to produce aproduct, thereby generating detailed time data; latching the detailedtime data at a given time in a data input signal; converting the latchedtime data into converted time data having a given data format;reproducing the converted time data in a same transmission path as thedata input signal; measuring a time ratio between recording andreproducing time data; controlling a reproduced clock signal accordingto the ratio; presetting the time data in a counter; and supplying thecontrolled reproduced clock signal to said counter to produce a count ofthe counter as a reproduced time code.
 5. A method according to claim 4,wherein said detailed time data include in a portion thereof informationrepresenting divisions of a prescribed carrier signal of the suppliedtime code, and a carrier signal of the reproduced time code is generatedusing said information representing divisions.
 6. A method according toclaim 4, wherein said given data format includes a history of recordedinformation including the time data at a beginning of the input signalwhich is successively recorded and position information thereof on arecording medium, and a search is controlled using the history when thetime code is reproduced.
 7. An apparatus for recording a time code,comprising;means for multiplying a supplied time code to produce aproduct, thereby generating detailed time data; means for latching thedetailed time data at a given time in a data input signal; means forconverting the latched time data into converted time data having a givendata format; and means for recording the converted time data in a sametransmission path as the path as the data input signal.
 8. An apparatusaccording to claim 7, further comprising means for detecting informationrepresenting divisions of a prescribed carrier signal of the suppliedtime code, said information being included in a portion of said detailedtime data.
 9. An apparatus according to claim 7, further comprisingmeans for producing a history of recorded information including the timedata at a beginning of the input signal which is successively recordedand position information thereof on a recording medium, and wherein saidhistory is included in said given data format.
 10. An apparatus forreproducing a time code, comprising:means for multiplying a suppliedtime code to produce a product, thereby generating detailed time data;means for latching the detailed time data at a given time in a datainput signal; means for converting the latched time data into convertedtime data having a given data format; means for reproducing theconverted time data in the same transmission path as the data inputsignal; means for measuring a time ratio between recording andreproducing time data; and controlling a reproduced clock signalaccording to the ratio; wherein the time data are preset in a counter,and the controlled reproduced clock signal is supplied to said counterto produce a count of the counter as a reproduced time code.
 11. Anapparatus according to claim 10, wherein said detailed time data includein a portion thereof information representing divisions of a prescribedcarrier signal of the supplied time code, and means for generating acarrier signal of the reproduced time code is controlled using saidinformation representing divisions.
 12. An apparatus according to claim10, wherein said given data format includes a history of recordedinformation including the time data at a beginning of the input signalwhich is successively recorded and position information thereof on arecording medium, and searching means is controlled using the historywhen the time code is reproduced.